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19-3663; Rev 0; 5/05
Push-Pull FET Driver with Integrated Oscillator and Programmable Clock Output
General Description
The MAX5077 is a +4.5V to +15V push-pull, current-fed topology driver subsystem with an integrated oscillator used in telecom module power supplies. The device drives two MOSFETs connected to a center-tapped transformer primary providing secondary-side, isolated, negative or positive voltages. The MAX5077 features a programmable accurate integrated oscillator with a synchronizing clock output to synchronize an external PWM regulator. A single external resistor programs the internal oscillator frequency from 50kHz to 1.5MHz. The MAX5077 incorporates dual MOSFET drivers with 3A peak drive currents and 50% duty cycle. The MOSFET drivers generate complementary signals to drive external ground-referenced n-channel MOSFETs. The MAX5077 clock output frequency is programmable by logic inputs to set the clock output to 1x, 2x, or 4x the MOSFET's driver frequency. The MAX5077 is available in a 14-pin exposed pad TSSOP package and is specified over the -40C to +125C operating temperature range.
Features
o Dedicated Current-Fed, Push-Pull Driver Subsystem o Oscillator Frequency Programmable from 50kHz to 1.5MHz o Single +4.5V to +15V Supply Voltage Range o 3A Peak Gate-Drive Current o 1mA Operating Current at 250kHz with No Capacitive Load o Selectable Synchronizing Clock Frequency for a Preceding PWM Stage o Thermally Enhanced 14-Pin TSSOP o -40C to +125C Operating Temperature Range
MAX5077
Ordering Information
PART TEMP RANGE -40C to +125C PIN-PACKAGE 14 TSSOP-EP* PKG CODE U14E-3
Applications
Current-Fed Power Supplies Power-Supply Building Subsystems Push-Pull Driver Subsystems
MAX5077AUD
*EP = Exposed paddle. Pin Configuration appears at end of data sheet.
Typical Operating Circuit
VIN VIN DRVH VOUT
SYNCIN PWM CONTROLLER VCC
CLK
MAX5077
VCC SEL1 I.C. NDRV1 NDRV2
DRVL GND
RT AGND DGND
SEL2 PGND
GND
________________________________________________________________ Maxim Integrated Products
1
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Push-Pull FET Driver with Integrated Oscillator and Programmable Clock Output MAX5077
ABSOLUTE MAXIMUM RATINGS
VCC to AGND, DGND, PGND.................................-0.3V to +18V PGND, DGND to AGND ........................................-0.3V to +0.3V SEL1, SEL2 to DGND .............................................-0.3V to +18V CLK, RT to AGND.....................................................-0.3V to +6V NDRV1, NDRV2 to PGND...........................-0.3V to (VCC + 0.3V) CLK Current......................................................................20mA NDRV1, NDRV2 Peak Current (200ns) ..................................5A NDRV1, NDRV2 Reverse Current (Latchup Current) .....500mA Continuous Power Dissipation (TA = +70C) 14-Pin TSSOP (derate 20.8mW/C above +70C) .....1667mW Operating Temperature Range .........................-40C to +125C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +12V, SEL1 = VCC, SEL2 = DGND, RRT = 124k, NDRV1 = NDRV2 = open, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SUPPLY Input Voltage Supply Range Static Supply Current Switching Supply Current Undervoltage Lockout UVLO Hysteresis OSCILLATOR Frequency Range Accuracy Oscillator Jitter CLK Output High Voltage CLK Output Low Voltage CLK Output Rise Time CLK Output Fall Time GATE DRIVERS (NDRV1, NDRV2) Output High Voltage Output Low Voltage Output Peak Current Driver Output Impedance Latchup Current Protection Rise Time Fall Time tR tF VOH VOL IP INDRV1 = INDRV2 = 100mA INDRV1 = INDRV2 = -100mA Sourcing and sinking NDRV_ sourcing 100mA NDRV_ sinking 100mA Reverse current at NDRV1/NDRV2 CLOAD = 2nF CLOAD = 2nF 3 1.8 1.6 400 10 10 3 2.6 VCC 0.3 0.3 V V A mA ns ns ICLK = 1mA ICLK = -1mA CCLK = 30pF CCLK = 30pF 35 10 7V VCC 15V 4.5V VCC 7V 4.1 3.5 fOSC (Note 2) fOSC = 250kHz, 6V VCC 15V (Note 3) 50 -8 0.6 5.0 5.0 50 1500 +10 kHz % % V mV ns ns VCC ICCST ICCSW VUVLO SEL2 = SEL1 = DGND, drivers not switching SEL2 = DGND, SEL1 = VCC, fOSC = 250kHz VCC rising 3 4.5 150 1 3.5 300 15.0 320 3 4 V A mA V mV SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Push-Pull FET Driver with Integrated Oscillator and Programmable Clock Output
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +12V, SEL1 = VCC, SEL2 = DGND, RRT = 124k, NDRV1 = NDRV2 = open, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SEL_ INPUTS Input Current Input High Voltage Input Low Voltage VIH VIL 0V VSEL_ VCC 3 2.5 2 1.5 1 A V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5077
Note 1: The MAX5077 is 100% tested at TA = TJ = +125C. All limits over temperature are guaranteed by design. Note 2: Use the following formula to calculate the MAX5077 oscillator frequency: fOSC = 1012 / (32 x RRT). Note 3: The accuracy of the oscillator's frequency is lower at frequencies greater than 1MHz.
Typical Operating Characteristics
(VCC = +12V, SEL1 = VCC, SEL2 = DGND, RRT = 124k, NDRV1 = NDRV2 = open, CLK = open.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5077 toc01
STATIC SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5077 toc02
SUPPLY CURRENT vs. CCLK
1.45 1.40 SUPPLY CURRENT (mA) 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 RRT = 124k
MAX5077 toc03
7 6 SUPPLY CURRENT (mA) 5 4 3 2 1 0 4 5 6 7 8 fOSC = 500kHz fOSC = 250kHz fOSC = 100kHz fOSC = 50kHz fOSC = 1.25MHz
170 160 STATIC SUPPLY CURRENT (A) 150 140 130 120 110 100 90 80 TA = -40C TA = +25C TA = +125C
1.50
9 10 11 12 13 14 15
4
5
6
7
8
9 10 11 12 13 14 15
0
20
40
60
80
100
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
CCLK (pF)
SUPPLY CURRENT vs. TEMPERATURE
MAX5077 toc04
CLK RISE TIME vs. SUPPLY VOLTAGE
45 40 CLK RISE TIME (ns) 35 30 25 20 15 10 5 0 36.5 4 5 6 7 8 9 10 11 12 13 14 15 -50 -25 CCLK = 30pF
MAX5077 toc05
CLK RISE TIME vs. TEMPERATURE
CCLK = 30pF 39.0 CLK RISE TIME (ns) 38.5 38.0 37.5 37.0
MAX5077 toc06
1.20 1.18 1.16 SUPPLY CURRENT (mA) 1.14 1.12 1.10 1.08 1.06 1.04 1.02 1.00 -50 -25 0 25 50 75 100 fOSC = 250kHz
50
39.5
125
0
25
50
75
100
125
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
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3
Push-Pull FET Driver with Integrated Oscillator and Programmable Clock Output MAX5077
Typical Operating Characteristics (continued)
(VCC = +12V, SEL1 = VCC, SEL2 = DGND, RRT = 124k, NDRV1 = NDRV2 = open, CLK = open.)
CLK FALL TIME vs. SUPPLY VOLTAGE
MAX5077 toc07
CLK FALL TIME vs. TEMPERATURE
MAX5077 toc08
OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
RRT = 124k OSCILLATOR FREQUENCY (kHz) 254 252 250 248 246 TA = +125C 244 242 TA = +25C TA = -40C
MAX5077 toc09 MAX5077 toc12 MAX5077 toc11
14 12 CLK FALL TIME (ns) 10 8 6 4 2 0 4 5 6 7 8 CCLK = 30pF
12 CCLK = 30pF 10 CLK FALL TIME (ns) 8 6 4 2 0
256
9 10 11 12 13 14 15
-50
-25
0
25
50
75
100
125
4
5
6
7
8
9 10 11 12 13 14 15
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
OSCILLATOR FREQUENCY vs. RRT
MAX5077 toc10
NDRV FREQUENCY vs. CLK FREQUENCY
800 700
MAX5077 WAVEFORM (fCLK:fNDRV = 1x, RRT = 124k)
10,000 OSCILLATOR FREQUENCY (kHz)
IGH
NDRV FREQUENCY (kHz)
, SE
500 400 300 200 100
L1
1000
=H
600
LOW
2=
SEL
100
L SE
H 2=
IG
H,
L SE
1=
L
OW
NDRV2 5V/div
SEL
2=
HIG
E H, S
L1
=H
IGH
NDRV1 5V/div
10 10 100 RRT (k) 1000
0 0 250 500 750 1000 1250 1500 2s/div CLK FREQUENCY (kHz)
CLK 5V/div
MAX5077 WAVEFORM (fCLK:fNDRV = 2x, RRT = 124k)
MAX5077 toc13
MAX5077 WAVEFORM (fCLK:fNDRV = 4x, RRT = 124k)
MAX5077 toc14
NDRV2 5V/div
NDRV2 5V/div
NDRV1 5V/div
NDRV1 5V/div
CLK 5V/div 2s/div 4s/div
CLK 5V/div
4
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Push-Pull FET Driver with Integrated Oscillator and Programmable Clock Output
Pin Description
PIN 1, 8 2 3 4, 14 5 6 7 9 10 11 12 13 EP NAME N.C. SEL1 CLK I.C. RT AGND DGND PGND NDRV1 NDRV2 VCC SEL2 EP No Connection. Must be left unconnected. CLK Frequency Ratio Select Input. Use SEL1 and SEL2 to set fCLK to fNDRV_ frequency ratio (see Table 1). Synchronizing Clock Output. Clock output with a 10mA peak current drive that can be used to synchronize an external PWM regulator. CLK/NDRV_ frequency has a 1x, 2x, or 4x ratio (see the Synchronizing Clock Output section). Connect to ground. Internal function. Oscillator Timing Resistor Connection. Bypass RT with a 1nF capacitor to AGND. Connect a resistor from RT to AGND to set the internal oscillator frequency. Analog Ground. Connect AGND to ground plane. Digital Ground. Connect DGND to ground plane. Power Ground. Connect to ground plane. Gate Driver 1. Connect NDRV1 to the gate of an external n-channel FET. Gate Driver 2. Connect NDRV2 to the gate of an external n-channel FET. Power-Supply Input. Bypass VCC to PGND with 0.1F||1F ceramic capacitors. CLK Frequency Divisor Input. Use SEL1 and SEL2 to set fCLK to fNDRV_ frequency ratio (see Table 1). Exposed Pad. Internally connected to DGND. Connect exposed pad to ground plane. FUNCTION
MAX5077
SEL1
MAX5077
UVLO 3.5V
VCC
SEL2 VCC 5V LDO DGND NDRV2 Q Q Q T-FF Q NDRV1 Q Q RT AGND OSC INTERNAL FUNCTION PGND I.C. I.C. N.C.
CLK
Figure 1. MAX5077 Functional Diagram _______________________________________________________________________________________ 5
Push-Pull FET Driver with Integrated Oscillator and Programmable Clock Output MAX5077
Detailed Description
The MAX5077 is a +4.5V to +15V push-pull, current-fed topology driver subsystem with an integrated oscillator for use in 48V module power supplies. The MAX5077 features a programmable accurate integrated oscillator with a synchronizing clock output that can be used to synchronize an external PWM stage. A single external resistor programs the internal oscillator frequency from 50kHz to 1.5MHz. The MAX5077 incorporates dual MOSFET drivers with 3A peak drive currents and a 50% duty cycle. The MOSFET drivers generate complementary signals to drive external ground-referenced n-channel MOSFETs. The MAX5077 CLK output frequency is programmable through logic inputs that set the fCLK:NDRV_ ratio to 1x, 2x, or 4x.
Table 1. CLK Output Frequency Selection
SEL2 Low Low High High
NDRV1
SEL1 Low High Low High
fCLK
fNRDV_
fCLK to fNDRV RATIO 1 2 4
NDRV1, NDRV2, and CLK disabled fOSC / 2 fOSC fOSC fOSC / 2 fOSC / 2 fOSC / 4
NDRV2 CLK OSC SEL2 = 0, SEL1 = 0
Internal Oscillator
An external resistor at RT programs the MAX5077's internal oscillator frequency from 50kHz to 1.5MHz. The MAX5077 NDRV1 and NDRV2 switching frequencies are one-half or one-fourth the programmed oscillator frequency with a nominal 50% duty cycle. Use the following formula to calculate the internal oscillator frequency: 1012 fOSC = 32 x RRT where fOSC is the oscillator frequency and RRT is a resistor connected from RT to AGND in ohms. Place a 1nF capacitor from RT to AGND for stability and to filter out noise. When the fCLK:fNDRV_ ratio is set to 4, the NDRV1 and NDRV2 switching frequency is limited to one-fourth f OSC . When operating the MAX5077 with the fCLK:fNDRV_ ratios set to 1 or 2 (see the Synchronizing Clock Output section), the NDRV1 and NDRV2 switching frequency is set to one-half fOSC. Synchronizing Clock Output The MAX5077 provides a buffered clock output that can be used to synchronize the oscillator input of a PWM controller. CLK is powered from an internal 5V regulator and sources/sinks up to 10mA. Two logic inputs (SEL2, SEL1) select CLK output frequency to 1x, 2x, or 4x with respect to NDRV1 and NDRV2 switching frequency (see Table 1 and Figure 2). Drive SEL2 and SEL1 low to disable NDRV1, NDRV2, and CLK outputs. There is a typical 30ns delay from CLK to NDRV_ output.
NDRV1 NDRV2 NDRV1 NDRV2
CLK OSC SEL2 = 0, SEL1 = 1
CLK OSC SEL2 = 1, SEL1 = 0
NDRV1
NDRV2
CLK
OSC SEL2 = 1, SEL1 = 1
Figure 2. MAX5077 CLK Timing Diagram 6 _______________________________________________________________________________________
Push-Pull FET Driver with Integrated Oscillator and Programmable Clock Output
Applications Information
Supply Bypassing
Pay careful attention to bypassing and grounding the MAX5077. Peak supply and output currents may exceed 3A when driving large MOSFETs. Ground shifts due to insufficient device grounding may also disturb other circuits sharing the same ground-return path. Any series inductance in the VCC, NDRV1, NDRV2, and/or GND paths can cause noise due to the very high di/dt when switching the MAX5077 with any capacitive load. Place one or more 0.1F ceramic capacitors in parallel as close to the device as possible to bypass VCC to PGND. Use a ground plane to minimize ground-return resistance and inductance. Place the external MOSFETs as close as possible to the MAX5077 to further minimize board inductance and AC path impedance.
Layout Recommendations
The MAX5077 drivers source and sink large currents that can create very fast rise and fall edges at the gate of the switching MOSFETs. The high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. Use the following PC board layout guidelines when designing with the MAX5077: * Place one or more 0.1F decoupling ceramic capacitors from VCC to PGND as close to the device as possible. Connect VCC and all ground pins to large copper areas. Place one bulk capacitor of 10F on the PC board with a low-impedance path to the VCC input and PGND of the MAX5077. * Two AC current loops form between the device and the gates of the driven MOSFETs. The MOSFET looks like a large capacitance from gate to source when the gate pulls low. The current loop is from the MOSFET gate to NDRV1/NDRV2 of the MAX5077, to PGND, and to the source of the MOSFETs. When the gate of the MOSFET is pulled high, the current is from the VCC terminal of the decoupling capacitor, to VCC of the MAX5077, to NDRV1/NDRV2, to the MOSFET gate and source. Both charging current and discharging current loops are important. Minimize the physical distance and the impedance in these AC current paths. * Keep the device as close to the MOSFET as possible.
MAX5077
Power Dissipation
Power dissipation of the MAX5077 is a function of the sum of the quiescent current and the output current (either capacitive or resistive load). Maintain the sum of the currents so the maximum power dissipation limit is not exceeded. The power dissipation (PDISS) due to the quiescent switching supply current (ICCSW) can be calculated as: PDISS = VCC x ICCSW For capacitive loads, use the following equation to estimate the power dissipation: PLOAD = 2 x CLOAD x VCC2 x fNDRV_ where C LOAD is the capacitive load at NDRV1 and NDRV2, VCC is the supply voltage, and fNDRV_ is the MAX5077 NDRV_ switching frequency. Calculate the total power dissipation (PT) as follows: PT = PDISS + PLOAD
_______________________________________________________________________________________
7
Push-Pull FET Driver with Integrated Oscillator and Programmable Clock Output MAX5077
Pin Configuration
TOP VIEW
Chip Information
TRANSISTOR COUNT: 1335 PROCESS: BiCMOS
N.C. 1 SEL1 CLK 2 3
14 I.C. 13 SEL2 12 VCC
I.C. 4 RT 5 AGND 6 DGND 7
MAX5077
11 NDRV2 10 NDRV1 9 PGND N.C.
*EP
8
TSSOP
*EXPOSED PADDLE CONNECTED TO DGND.
8
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Push-Pull FET Driver with Integrated Oscillator and Programmable Clock Output
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
TSSOP 4.4mm BODY.EPS
MAX5077
XX XX
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY, EXPOSED PAD
21-0108
E
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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